Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated.
One manner of reducing power consumption in an integrated circuit is to cause some or all of the integrated circuit to be placed into a given one of multiple available low power states. However, there is a latency and performance penalty associated with entry into and exit from a low power state, which can have adverse impacts. For example, information present in the integrated circuit may be lost during the low power state, such that undesired overhead is incurred when the integrated circuit exits the low power state.